1. Field of the Invention
The present invention relates to the field of semiconductor integrated-circuit (IC) manufacturing, and in particular a technique of providing uniform etch depth by using ion implantation and a timed etch.
2. Description of the Related Art
The vertical dimensions of semiconductor devices (e.g. capacitors, transistors) with non-planar surfaces are often defined simply by a timed etch of a homogeneous dielectric (e.g. oxide) material that serves to electrically isolate semiconductor device regions. For example, FIG. 1A illustrates a cross-sectional view of a patterned silicon layer 101 and dielectric areas 102 that can provide electrical isolation. During the process of forming devices in patterned silicon layer 101, dielectric areas 102 can be etched. Generally, this etch has high selectivity between materials, thereby etching dielectric areas 102 much more quickly than patterned silicon layer 101. In some embodiments, a mask can be used to further protect patterned silicon layer 101 during the etching of dielectric areas 102.
Unfortunately, the etch rate across a wafer is typically not perfectly uniform due to equipment imperfections, variations in IC pattern density, and/or inherent conditions associated with the etch process being used. For example, it is not uncommon to have an etch rate variation of 10% across a wafer. The etch rate variation causes non-uniform etching of dielectric areas 102. Non-uniformity of etched dielectric areas 102A, as shown in FIG. 1B, results in variations of vertical device dimensions across a chip, within a wafer, or even from wafer to wafer. In turn, these vertical device dimension variations may result in significant device and circuit performance variations, which is highly undesirable.
Therefore, a need arises for a technique for providing uniform etch depth to minimize device and circuit performance variations.